The development of computer graphics systems creates the need for fast memories capable of storing huge amounts of data, such as 3-D graphics data. Among such memories are cached memories developed to improve DRAM main memory performance by utilizing a faster SRAM cache memory for storing the most commonly accessed data. For example, U.S. Pat. No. 5,566,318 discloses an enhanced DRAM that integrates a SRAM cache memory with a DRAM on a single chip. Sense amplifiers and column write select registers are coupled between the SRAM cache and the DRAM memory array. A column decoder is associated with the SRAM cache for providing access to the desired column of the SRAM. A row decoder is associated with the DRAM memory array to enable access to particular rows of the DRAM. Input/output control and data latches receive data from the SRAM to provide data output via data input/output lines. The current row of data being accessed from the DRAM memory array is held in the SRAM cache memory. Should a cache "miss" be detected, the entire cache memory is refilled from the DRAM memory array over a DRAM-to-cache memory bus.
As a way of improving speed and performance of a RAM, a dual-port RAM has been developed which enables two separate input/output ports to access the memory array. However, the dual-port RAM cannot provide effective control of data input and output because its ports are not interchangeable. For example, data traffic cannot be redistributed between the ports when one of them is overloaded and the other is underloaded.
Referring to FIG. 1, a dual-port RAM 2 comprises IO ports A and B that input and output data to and from the RAM 4, and control input/output operations. A DRAM 4 is used as a main memory, whereas the most commonly accessed data are retained in a SRAM cache memory 6. Data transfers between the ports A and B and the DRAM main memory 4 are carried out via the SRAM 6 split into portions 6A and 6B. A data block supplied via port A is held in the SRAM 6A before being written into the DRAM 4. Similarly, a data block from port B is supplied to the SRAM 6B before being transferred to the DRAM 4.
Port A has access only to the SRAM 6A, whereas port B is able to access only the SRAM 6B. Therefore, the most current data is stored in the DRAM 4 rather than in the SRAM 6. New data entered into one SRAM portion must be written into the DRAM 4. Once the DRAM 4 is updated, the new data is then entered into the other SRAM portion in the next write cycle. Thus, to keep both SRAM portions current, data transfers from one SRAM portion to the DRAM and from the DRAM to the other SRAM portion are required.
To improve the bandwidth of data input/output operations in a multi-port RAM, it would be desirable to enable each port of the RAM to access any SRAM location.
Also, it would be desirable to provide a multi-port RAM having interchangeable ports that enables any of the ports to access the most current data at any time.